SystemVerilog • STA
Custom CPU
A multi-cycle CPU built from scratch with custom control, datapath design, instruction sets, and verificaiton methods.
Portfolio
My name is Ramtin Soleymani.
I’m an Electrical Engineering student focused on ASIC Design, RTL Design, FPGA Testing, and Design Verification.
Highlighted Projects
Selected projects.
UVM • FPGA
FPGA Stopwatch
A stopwatch with debounced inputs, modular RTL blocks, and a structured verification flow for the counter and display logic.
Embedded C/C++
Media Centre
An embedded Cortex-M3 project with an LCD interface, media controls, and joystick-driven games built on the system.
AI Model • Python Scripts
Role Matcher
A resume-to-job platform that combines OCR, filtering, vector similarity, and cloud-backed search for stronger job matching.
Accomplishments
A few highlights.
Hydro One Co-op
Supported engineering work, coordination, and technical tracking in a fast-moving utility environment.
Part-Time Intern + Full Time Student
Balanced an electrical design engineering internship throughout my electrical engineering studies while continuing to build technical projects.
Timing Closure
Modified the design, so that the project at hand could fit in the 100 MHz Clock Cycle of my FPGA.
UVM Verification
Built UVM components and standard verification flows to verify design more thoroughly before deployment.
CPU Design
Designed a multi-cycle CPU from scratch, giving me a great understanding of RTL Design, Design Verification, and Computer Architecture.
Dean’s List
Earned the Fall 2025 Dean’s List in the Faculty of Engineering and Architectural Science during final year.
Contact
Let’s connect.
I’m open to new graduate opportunities in ASIC design, RTL Design, Design Verification, and FPGA-focused hardware roles.