SystemVerilog • STA
Custom CPU
A multi-cycle CPU built from scratch with custom control, datapath design, instruction support, and FPGA validation.
Portfolio
My name is Ramtin Soleymani.
I’m an Electrical Engineering student focused on ASIC and RTL design, FPGA implementation, DV, and computer architecture.
Highlighted Projects
Selected projects.
UVM • DV
FPGA Stopwatch
A stopwatch with debounced inputs, modular RTL blocks, and a structured verification flow for the counter and display logic.
Embedded C/C++
Media Centre
An embedded Cortex-M3 project with an LCD interface, media controls, and joystick-driven games built around clear system structure.
AI Model • Full-Stack
Role Matcher
A resume-to-job platform that combines OCR, filtering, vector similarity, and cloud-backed search for stronger job matching.
Accomplishments
A few highlights.
Hydro One Co-op
Supported engineering work, coordination, and technical tracking in a fast-moving utility environment.
Work + Study
Balanced part-time work with final-year engineering studies while continuing to build technical projects.
Timing Closure
Iterated on RTL and implementation choices to move designs toward cleaner FPGA timing and more stable bring-up.
UVM Verification
Built UVM components and structured verification flows to check functionality more thoroughly before deployment.
CPU Design
Designed a configurable CPU from scratch, shaping the datapath, control logic, instruction support, and hardware validation flow.
Dean’s List
Earned the Fall 2025 Dean’s List in the Faculty of Engineering and Architectural Science during final year.
Contact
Let’s connect.
I’m open to new graduate opportunities in ASIC design, RTL, DV, and FPGA-focused hardware roles.